Semiconductor devices are manufactured by repeatedly performing various processes such as a film-forming process, an etching process and the like on a semiconductor wafer. According to recent demands for high speed of a semiconductor device, miniaturization of a wiring pattern, and high integration of a semiconductor device, a wiring requires a reduction in resistance of a wiring (improvement in conductivity) and an improvement in electro-migration resistance.
In order to cope with this point, copper (Cu) that has both higher conductivity (lower resistance) and better electro-migration resistance than aluminum (Al) or tungsten (W) which have been used for wirings.
A method of forming a Cu wiring was proposed which includes: forming a barrier film formed of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or the like on an entire interlayer dielectric film with a trench or hole formed therein using a plasma sputtering as PVD (Physical Vapor Deposition); forming a Cu seed film on the barrier film using plasma sputtering; plating a copper film on the copper seed film to completely bury the trench or hole; and removing the extra copper thin film and the extra barrier film on the surface of the wafer using CMP (Chemical Mechanical Polishing).
However, as design rules of semiconductor devices are gradually miniaturized, a current density is increased. This fails to sufficiently secure an electro-migration resistance even though Cu is used as a material of the wiring. Therefore, a demand is increased for developing a technology which improves the electro-migration resistance of the Cu wiring.
To meet such a demand, there has been proposed a technology for improving an adhesion between a Cu wiring and a dielectric cap (SiCN cap) film formed thereon by segregating alloy components such as Mn or Al toward a region between the Cu wiring and the dielectric cap film using a Cu alloy such as Cu—Mn or Cu—Al as a seed layer, instead of a Cu seed film. In addition, there has been proposed a technology for improving an adhesion between the Cu wiring and the dielectric cap film by selectively forming a metal cap on a surface of the Cu wiring.
However, alloy components contained in the Cu alloy used as the seed layer and impurities contained in the Cu-plated film are introduced into the Cu wiring, thus resulting in an increased wiring resistance.
In addition, forming a metal cap on the Cu wiring requires selectively forming the metal cap only on the Cu wiring in order to prevent a leak current from being generated between wirings. As such, an increased number of processes is required to secure the selectivity, thus leading to an increase in cost.
In addition, as described above, as the design rules of the semiconductor devices are gradually made finer, a width of a trench or a diameter of a hole amounts to tens of nm. When the barrier film or the seed film is formed in a narrow recess such as a trench or hole using plasma sputtering, and subsequently, the trench or hole is buried by the Cu plating, the trench or the hole is not completely buried with Cu, thereby generating voids.